IBM announced that moving from a 5nm process to 2nm allows 50bn transistors on a fingernail-size chip rather than 30bn. But 30bn x (5/2) x (5/2) = 187.5bn not 50bn.
For the past 20-odd years the die-shrink node nomenclature (5nm, 2nm, etc.) has had no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors and as such is no indicator of mathematical scaleability. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved...
For the past 20-odd years the die-shrink node nomenclature (5nm, 2nm, etc.) has had no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors and as such is no indicator of mathematical scaleability. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density, increased speed and reduced power consumption.
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